Design and implementation of image kernels using reversible logic gates
Also Available Domains Xilinx Vivado|Xilinx ISE
Abstract
In this project we have implemented image kernels based on reversible logic gates which is the first attempt to make reversible gate based filter implementations. In this study, we presents the implementation of image kernels used for filtering and enhancing the images using reversible logic gates, a first in reversible logic literature. Image enhancement/filtering is achieved by performing convolution of an image with a filter kernel. In this particular work we proposes reversible logic based design and implementation of six filter kernels. The filter kernels implemented are Gaussian blur, Laplacian outline, Sobel, Emboss, Sharpen and Prewitt edge detection. The kernels are implemented individually using reversible logic gates and the designs are measured in terms of Area, delay and analyze the difference among the filter implementations and compare the parameter results among the six filters. The synthesis and simulation verification is carried out using Xilinx ISE14.7/ Vivado.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
· Xilinx ISE/Vivado Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modelling styles in Verilog
o Data Flow modelling
o Structural modelling
o Behavioural modelling
o Mixed level modelling
- Introduction to Arithmetic circuits
- About reversible logic
- Knowledge on adder, divider, mux, multiplier architectures
- Different reversible gates
- Knowledge on adder, divider, mux, multiplier designs using reversible gates
- About quantum computing
- About image kernals and its types
- Applications in real time
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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