Design and Implementation of High Speed Radix-2 CSD Based Floating Point Multiplier

In this project, we propose a novel technique to multiply two unsigned binary numbers through a radix-2 CSD based approach. Since last few decades, Analog systems or especially Digital systems are fabricated with ICs. These systems are basically having multiplier as fundamental element. Thus design of multiplier is so important that digital systems will be designed efficiently. Furthermore floating point multipliers are preferable over normal multipliers, because unlike normal multipliers floating point multipliers would support very small and even very large numbers. Earlier many researchers focused on design of floating point multipliers which results to many algorithms such as Booth algorithm, Vedic sutras and CSD algorithm. Here, modified CSD algorithm is proposed which is having lower delay i.e. higher speed in comparison with existing CSD algorithm due to the usage of pipeline concept. All the algorithms of floating point multiplier discussed here are designed using verilog HDL and targeted on Xilinx Vivado 2018.3.