Design and Implementation of an Adaptive FPGA-Based Traffic Light Control System Using Verilog

Project Code :TVMAFE702

Objective

Adaptive Signal Timing Based on Traffic Conditions • Dynamically adjust traffic light durations (green, yellow, red) according to real-time traffic density rather than using a fixed timer. • Use sensors (vehicle detectors) to estimate traffic flow and modify signal phases to reduce congestion.

Abstract

This paper describes an adaptive traffic light control system using FPGAs and Verilog. It features a 6-state finite state machine that adjusts signal timing in real time based on traffic, pedestrian, and emergency inputs. The system achieves sub-10 ns latency, reduces vehicle delay by 36%, and uses 35% less power than microcontroller-based systems. Simulations confirm correct operation and fault recovery. The design is scalable, energy-efficient, and well-suited for smart city traffic management

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Xilinx ISE Tool/Xilinx Vivado

HDL: System Verilog

Learning Outcomes

Understanding of traffic light control logic and adaptive systems.
Knowledge of Verilog HDL for FSM-based digital design.
Hands-on experience with FPGA implementation and simulation.
Ability to design real-time control systems using hardware logic.
Understanding of adaptive algorithms in embedded systems.
Development of practical skills applicable to smart traffic and automation projects.