Design and Implementation of a low power high speed full adder cell for low power applications

Project Code :TVMABE265

Objective

The primary objective appears to be designing and implementing a low power, high speed full adder cell optimized for low power applications

Abstract

The one-bit full adder cell is a fundamental component of computational circuits, widely utilized in arithmetic logic units (ALUs). Significant advancements have been made in the architecture and functionality of full adder circuit designs. This paper details the implementation of two 1-bit full adder designs using 90nm CMOS technology: a conventional CMOS adder cell and a Transmission Gate Logic (16-T) adder cell. Simulation results demonstrate that the proposed adder cells surpass existing designs in terms of power consumption, delay, and power delay product (PDP).

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Specifications

Specifications:

Software Requirements:

• Xilinx ISE Tool

• HDL: Verilog

Demo Video

https://youtu.be/AAJnbXHUaIw

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Front End Domains

Arithmetic Core
Communications
DSP Core
FPGA

Back End Domains

Core Memories
Low Power VLSI
Transistor Logic
Nano Technology

Tools

Xilinx ISE
FPGA
Cadence EDA
Xilinx Vivado

Others

Matlab Interfacing