Design and Implementation of a 4-Bit Carry Select Adder using MTCMOS-Based Ripple Carry Adder with 10T Full Adders in 90nm Technology

Also Available Domains Cadence EDA|Nano Technology|Low Power VLSI

Project Code :TVMABE378

Objective

Design a Low-Power 10-Transistor Full Adder • Implement a 10-transistor full adder (10 T FA) optimized for low leakage and power consumption. • Use MTCMOS (multi-threshold CMOS) technique to minimize leakage power: employ high-VT transistors in idle paths and low-VT transistors in speed-critical paths. MTCMOS is a known method to reduce leakage in CMOS circuits. • Target the design for 90 nm CMOS technology, ensuring that the transistor sizing and threshold voltage selection are appropriate for that process node.

Abstract

Low-power and high-speed arithmetic units are essential for modern VLSI systems, especially in energy-constrained applications. This work presents the design and implementation of a 4-bit Carry Select Adder (CSA) using an MTCMOS-based Ripple Carry Adder (RCA) constructed with 10-transistor (10T) full adders in 90 nm CMOS technology. The proposed architecture exploits the speed advantage of CSA while reducing leakage power through Multi-Threshold CMOS (MTCMOS) techniques. High-threshold sleep transistors are employed to minimize standby power, and the compact 10T full adder design reduces area and switching activity. Simulation results demonstrate significant improvements in power consumption, delay, and power–delay product (PDP) compared to conventional CMOS adder implementations, making the design suitable for low-power VLSI and portable digital systems.

Index Terms: Carry Select Adder (CSA), MTCMOS, Ripple Carry Adder (RCA), 10T Full Adder, Low-power VLSI, 90 nm CMOS technology.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Specifications

Software Requirements:

· Cadence tool

· Technology files: 45nm

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

· Understand the working principle of Carry Select Adders (CSA) and Ripple Carry Adders (RCA).

· Learn the design and advantages of 10-transistor (10T) full adders for low-power operation.

· Gain knowledge of MTCMOS techniques for leakage power reduction.

· Analyze the impact of technology scaling (90 nm) on power, delay, and area.

· Evaluate performance metrics such as power, delay, and power–delay product (PDP).

· Apply low-power design techniques in VLSI arithmetic circuits and SoC applications

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

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QCA
Xilinx Vivado
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