Design and Implementation of a 4-Bit Carry Save Adder Using MTCMOS-Based Ripple Carry Adder with 10T Full Adders in 90nm Technology

Project Code :TVMABE791

Objective

This work presents the design and implementation of a 4-bit Carry Save Adder (CSA) utilizing a Multi-Threshold CMOS (MTCMOS)-based Ripple Carry Adder (RCA) constructed with 10-transistor (10T) full adders in 90nm technology. With the increasing demand for high-speed and low-power arithmetic circuits in digital systems, efficient adder architectures play a crucial role in enhancing overall system performance

Abstract

In the proposed design, MTCMOS technique is employed to minimize leakage power by using high-threshold transistors as sleep devices, effectively reducing standby power consumption. The 10T full adder cells are optimized to achieve a balance between reduced transistor count, power efficiency, and speed. By integrating CSA with an MTCMOS-based RCA, the design achieves fast intermediate computation and efficient final carry propagation. The circuit is implemented and simulated in 90nm CMOS technology, and its performance is evaluated in terms of power consumption, delay, and power-delay product (PDP). Results demonstrate significant improvements in energy efficiency and speed compared to conventional CMOS adder designs, making it suitable for low-power and high-performance VLSI applications.

Keywords

Carry Save Adder, MTCMOS, Ripple Carry Adder, 10T Full Adder, Low Power, 90nm CMOS, VLSI Design

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

· Tool Used: Cadence EDA tools for schematic and simulation

· Technology Node:180nm CMOS process.

· Design Elements: complementary compound push–pull pair (PMOS + NMOS), input matching network, L1 & L2 (0.5 pH–10 pH) inductors, high-value output load (RL, 100 kΩ–1 MΩ), biasing/level-shift network, feedback/compensation path, input/output coupling and decoupling capacitors, thermal-stabilization circuitry, and symmetric/layout considerations for reduced mismatch

· Optimization Goal: minimize circuit complexity and parasitics (transistor and passive count) while preserving ultra-wideband large-signal gain, low output noise, high temperature stability, and linearity across the desired cutoff range (e.g., maintain cutoff from ≈18.21 kHz up to hundreds of GHz in simulation) with low power consumption (~69 mW)v

Learning Outcomes

• Understanding of Carry Save Adder Architecture

• Knowledge of Ripple Carry Adder Design

• Application of MTCMOS Technique for Leakage Reduction

• Design of Low-Transistor Full Adders (10T)

• Performance Analysis Using Power, Delay, and PDP

• Hands-on Experience with VLSI Design Tools

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice