Design and Implementation of 5-Stage Pipelined RISC-V Processor

Project Code :TVMAFE763

Objective

The objective of the “Design and Implementation of a 5?Stage Pipelined RISC?V Processor” is to design, implement, and evaluate a 32?bit RISC?V core based on the RV32I instruction set architecture using a classic five?stage pipeline (instruction fetch, decode, execute, memory access, write back) with hazard control and forwarding logic to increase instruction throughput, improve operating frequency, and reduce power consumption compared to a single?cycle processor, and to realize the design on an FPGA platform for performance validation.

Abstract

This project presents the design and implementation of a 32-bit RISC-V processor using Verilog Hardware Description Language (HDL). The processor is based on the RISC-V RV32I instruction set architecture, emphasizing simplicity, modularity, and scalability. The design incorporates essential components such as the program counter, instruction memory, register file, arithmetic logic unit (ALU), control unit, and data memory. A single-cycle datapath architecture is implemented to execute instructions efficiently with reduced design complexity

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements

• Xilinx Vivado / ISE

• Verilog HDL / ModelSim

Hardware Requirements

• Xilinx FPGA (Spartan / Virtex)

• Logic Analyzer

Learning Outcomes

• Dual-Tier LFSR Architecture Design

• Low Power BIST Methodology

• Parameterizable HDL Design

• Transition Activity Analysis in VLSI

• Power-Aware DFT Techniques

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice