Design and Implementation of 32-Bit MIPS-Based Softcore Processor with Enhanced Instruction Set on FPGA

In this paper, the 32-bit MIPS HDL processor has been devised to serve the purpose of running Symmetric and Overloaded Instruction Set (SOMA) on an FPGA. The SOMA architecture is unique in its overloaded and branching instructions. With a Verilog processor developed based on the SOMA design, the feasibility of SOMA on hardware is proven. This design has evident optimizing resource utilization. The findings make significant contributions to the improvement of the methodologies used in designing processors and that FPGAs are less expensive and practical Hardware platforms to test the designs. A 32-bit processor is implemented in HDL with 20 instructions and can handle memory of 32 registers. Design is tested and implemented on Xilinx DDR 4 FPGA board. Synthesis results were evident that the SOMA register-integer class and Branch class are practical.