Design and Hardware Implementation of Polar Codes Using Verilog for Digital Systems

Polar codes, introduced by Arkan, are capacity achieving error-correcting codes and have been adopted in a new 5G radio (NR) for encoding control channels due to their structured construction and efficient decoding. De spite extensive theoretical research, many existing designs lack attention to practical hardware constraints, particularly latency and synthesis complexity. Decoder architectures often struggle with scalability and parallelism, resulting in increased area and power consumption issues critical in embedded and resource-constrained environments. This work proposes a fully synthesized verilog RTL implementation of a 64-bit polar code encoder and a corresponding successive cancellation (SC) decoder, optimized for low-power, high-throughput digital systems. The encoder leverages Kronecker-based generator matrices for recursive encoding, while the SC decoder uses a depth-first traversal with hardware-efficient soft-decision logic. The design is modeled, synthesized, and validated on a 45 nm CMOStechnology node using Xilinx Vivado. Area, power, and delay analysis confirm the design’s efficiency and suitability for real-time digital communication systems. 

Index Terms—Polar codes, Verilog, 5G NR, Hardware im plementation, Successive cancellation decoding, Digital VLS