DESIGN AND COMPARISON OF VEDIC MULTIPLIER USING CMOS AND GDI TECHNIQUE IN 90 nm TECHNOLOGY

Multipliers are in high demand due to their wide range of applications and are essential components in almost every circuit for performing basic operations. While CMOS technology is traditionally used for designing multipliers, alternative techniques like GDI can support low-power designs. With increasing emphasis on reducing delay, quick multiplication designs have gained prominence. Vedic mathematics, known for its fast calculations and simplicity, is often utilized, particularly the “Urdhva Tiryagbhyam” sutra among the 16 available sutras. This work compares a two-bit multiplier designed in 90nm technology using Cadence Virtuoso with a GDI-based two-bit multiplier. The fundamental components are designed first and integrated into a Vedic multiplier structure, which can be extended to higher-bit designs. Despite challenges, Vedic mathematics simplifies complex designs for efficient implementation.

Index Terms— Vedic Multiplication, pipelining, real-time processing