DESIGN AND COMPARISON OF VEDIC MULTIPLIER USING CMOS AND GDI TECHNIQUE IN 90 nm TECHNOLOGY

Also Available Domains Cadence EDA|Transistor Logic

Project Code :TVMABE278

Objective

the paper aims to compare and contrast the design and performance of Vedic multipliers implemented using CMOS and GDI techniques in 90nm technology, focusing particularly on power consumption and design complexity.

Demo Video

https://youtu.be/ECGZTQsR0v4?si=YdflolkbK31sI3n5

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Related Topics
  • Arithmetic Core
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  • DSP Core
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  • FPGA
  • Cadence EDA
  • Xilinx Vivado
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