DESIGN AND COMPARISON OF VEDIC MULTIPLIER USING CMOS AND GDI TECHNIQUE IN 90 nm TECHNOLOGY
Also Available Domains Low Power VLSI|Transistor Logic
Project Code :TVMABE277
Objective
the paper aims to compare and contrast the design and performance of Vedic multipliers implemented using CMOS and GDI techniques in 90nm technology, focusing particularly on power consumption and design complexity.
Demo Video
https://youtu.be/ECGZTQsR0v4?si=YdflolkbK31sI3n5
Request for Video
Related Projects
Related Topics
Paper PublishingRequest Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
