Design and Analysis of Optimized Dynamic Comparator Circuit for Low Power and High Speed Applications

This paper presents the design and analysis of an optimized dynamic comparator circuit aimed at achieving low power consumption and high-speed operation for modern VLSI applications. Dynamic comparators are critical building blocks in analog-to-digital converters (ADCs), memory sense amplifiers, and high-frequency signal processing systems. The proposed comparator employs an optimized transistor-level architecture that reduces internal node capacitance and minimizes short-circuit current paths during switching transitions. By carefully tailoring the sizing of NMOS and PMOS transistors and introducing a modified regenerative latch structure, the circuit achieves a significant reduction in power delay product (PDP) while maintaining robust comparison accuracy even at low supply voltages. The design is implemented and simulated using 45 nm CMOS technology, and results demonstrate improved speed and energy efficiency compared to conventional double-tail and StrongARM comparator topologies. The proposed architecture is well suited for high-speed ADCs, data converters, and low-power sensor interface circuits.

Index Terms—Dynamic comparator, low power, high speed, CMOS technology, power delay product, regenerative latch, ADC, VLSI design, 45 nm technology, optimized circuit design