Design and Analysis of Low-Power High Performance 4-Bit Parallel Shift Register using Retentive True Single Phase Clocked D-Flip Flop
Also Available Domains Cadence EDA
Project Code :TVPGTO844
Objective
The proposed design of the 4-bit PIPO shift register is designed using TSPC flip-flop and its operation and performance is discussed below 1V operating voltage to yield minimal power consumption.
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