DESIGN AND ANALYSIS OF LOW-POWER AND AREA EFFICIENT MASTER-SLAVE FLIP-FLOP

 In this paper, a novel master-slave flip-flop, featuring 15 transistors and a single-phase clock, is introduced, utilizing topological and adaptive coupling techniques. The proposed flip-flop circuit (PFC), implemented using 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology, outperforms other logic-structured flip-flops in terms of efficiency. Notably, the PFC demonstrates significant improvements in average power consumption compared to the Adaptive Data Track Flip-Flop (ADTFF), Hybrid Flip-Flop (HFF), 18-Transistor Single-Phase Clocked (18TSPC) flip-flop, Logic Structured Reduction Flip-Flop (LSRFF), and Topologically Compressed Flip-Flop (TCFF). Additionally, the PFC shows enhancements in C-to-Q delay and power-delay product (PDP), operates efficiently within a clock frequency range of up to 1 GHz, and minimizes the total area by reducing the number of PMOS transistors