Design and analysis of hybrid 10T adder for low power applications

This study presents a novel 10-transistor (10T) hybrid full adder architecture designed for ultra-low power applications using 45nm CMOS process technology. The design employs an energy-efficient hybrid logic multiplexer approach incorporating Gate Diffusion Input (GDI) logic, aiming to reduce both power consumption and chip area while maintaining performance. The proposed architecture features level restoration carry logic that ensures full swing output voltage, addressing the voltage degradation issues commonly found in conventional 10T adder designs. Comprehensive simulations were conducted using Mentor Graphics tools at various supply voltages (0.8V and 1.2V), and the results demonstrate significant improvements over existing full adder designs, including a 65% reduction in transistor count compared to traditional CMOS logic adders and a 37% reduction compared to transmission gate adders. The proposed design achieves at least 80% enhancement in power-delay product (PDP) parameters when compared to existing architectures, with the level restoration technique-based version consuming 13% less power and exhibiting 90% less delay than the version without level restoration, making it highly suitable for resource-constrained, energy-efficient digital systems.

KEYWORDS:   Hybrid full adder ,  10T adder , Low power design, CMOS technology, Gate Diffusion Input (GDI) logic , Level restoration technique , Ultra-low voltage (ULV).