Design and Analysis of DT-LFSR for Low Power BIST Applications

Project Code :TVMAFE798

Objective

Abstract

Linear Feedback Shift Registers (LFSRs) are extensively used as test pattern generators in Built-In Self Test (BIST) architectures due to their low hardware overhead and pseudorandom sequence generation. However, the high switching activity between successive test vectors generated by conventional LFSRs results in increased dynamic power consumption during test mode. This paper proposes a Dual-Tier LFSR (DT-LFSR) architecture designed to reduce bit transitions and lower power dissipation in BIST applications. The proposed architecture splits the conventional LFSR into two tiers with an intermediate flip-flop. Implemented and verified in Xilinx Vivado 2015.3, the DT-LFSR demonstrates a 50% reduction in bit transitions compared to traditional LFSRs. Results confirm superior power efficiency without compromising fault coverage, making it a practical solution for power-aware BIST design in VLSI circuits.

Keywords: DT-LFSR, Dual-Tier LFSR, BIST, Low Power, Test Pattern Generator, Switching Transitions, VLSI Testing, Xilinx Vivado

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements

• Xilinx Vivado / ISE

• Verilog HDL / ModelSim

Hardware Requirements

• Xilinx FPGA (Spartan / Virtex)

• Logic Analyzer

Learning Outcomes

• Dual-Tier LFSR Architecture Design

• Low Power BIST Methodology

• Parameterizable HDL Design

• Transition Activity Analysis in VLSI

• Power-Aware DFT Techniques

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice