DESIGN AND ANALYSIS OF DADDA MULTIPLIER USING APPROXIMATE 4-2 COMPRESSOR
Objective
By creating a DADDA multiplier using approximate 4-2 compressors, this work aims to contribute to the development of more sustainable and adaptable digital systems. This design could enable the widespread adoption of edge computing and IoT devices in various applications where precise arithmetic is not always necessary but energy efficiency is paramount.
Abstract
This paper presents a novel method for designing approximate multipliers using dual-stage 4:2 compressors. We explore two unique approximate compressors that enhance performance while streamlining the multiplication process. By incorporating these compressors into a 16 x 16 Dadda multiplier architecture, we achieve significant improvements in power efficiency and processing speed, with acceptable accuracy trade-offs. Extensive simulations confirm the effectiveness of our design, especially in resource-constrained environments. Our findings indicate that this innovative approach can boost computational efficiency across multiple fields. This work sets the stage for future research in approximate computing techniques.
Keywords— Area, Approximate computing, Compressor, Multimedia, Multiplier.
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Block Diagram
Specifications
Software Requirements:
- Tool: Cadence Virtuoso
- Technology: GPDK 45nm
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
· Introduction to Analog & Digital Electronics
· Advantages & Applications of Oscillator.
· Basics of VCO
o Different configurations of VCO
· Knowledge on Ring Oscillator
· Design of oscillator in Cadence
· Analysis of simulation results & Outputs
· Scope of oscillator in today’s world.
· Real time applications of oscillator.
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