Design & Analysis of full adders using adiabatic logic

This paper presents a comprehensive design and analysis of a modified full adder circuit that integrates XOR gates and 2:1 multiplexers utilizing pass transistor logic, combined with PFAL adiabatic logic style. The primary objective is to enhance the performance and power efficiency of arithmetic operations in digital circuits.

The proposed modified full adder leverages the strengths of XOR gates and multiplexers to achieve high-speed and low-power operation. The use of pass transistor logic in the design improves circuit efficiency by reducing power consumption compared to traditional static CMOS logic. The PFAL adiabatic logic style further contributes to power savings by minimizing energy dissipation during the switching process, thus making it well-suited for energy-constrained applications. Therefore these paper we are going to implement ripple carry adder for 4 bits using with PFAL logic full adder circuit on the tanner eda tool.

Keywords:Full adder, PFAL logic, CMOS &  Pass Transistor Logic(PTL) & Ripple carry adder.