Design a novel architecture of flash ADC using Memristor based encoder

In this paper, Flash Analog to digital converter is implemented whose resolution is 3-bits. The designed Flash ADC consists of a 3-stage magnitude comparators, memristor based encoder and the entire design is carried out using Lt-spice tool. The reference voltage applied to the resistive ladder network is 1.2V. A two-stage pre-amplifier is used as a comparator in the flash ADC. The major problem that usually appears in flash ADC is as the number of resolution bits increases, the Area, as well as the power consumption of the circuit, also increases. In this paper, we principally concentrated to lessen the power consumption of the ADC by optimizing encoder circuitry. With the purpose of reducing power consumption, Encoder is implemented using MRL. Performance parameters of Flash ADC such as delay as well as average power are calculated and compared.