Design a Low Power 8-bit Reversible Parallel Binary AdderSubtractor
Also Available Domains Arithmetic Core|Xilinx Vivado
Abstract
Reversible Logic is becoming more and more prominent technology
having its applications in Low Power CMOS, Quantum Computing, Nanotechnology,
and Optical Computing. Reversibility plays an important role when energy
efficient computations are considered. In this paper, Reversible eight-bit
Parallel proposed. In all the three design approaches, the full Adder and
Subtractors are realized in a single unit as compared to only full Subtractor
in the
existing design. The performance analysis is verified using number reversible
gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible
eight-bit Parallel Binary
Adder/Subtractor Binary Adder/Subtractor with Design.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Specifications
Hardware requirement
Processor - Pentium –III
Speed - 1.1 GHz
RAM - 1 GB (min)
Hard Disk - 40 GB
Floppy Drive - 1.44 MB
Key Board - Standard Windows Keyboard
Mouse - Two or Three Button Mouse
Monitor - SVGA
Software requirements
v Operating System :Windows95/98/2000/XP/Windows7
v Front End : Modelsim 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation
v This software’s where Verilog source code can be used for design implementation.
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to binary adders
- Writing Verilog code.
- Introduction to Combinational circuits.
- Knowledge on parallel binary adder.
- Applications in real time
· Xilinx tool for writing code, synthesis and simulation
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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