Decoder Reduction Approximation Scheme for Booth Multipliers

Also Available Domains Testing

Project Code :TVMAFE614

Objective

Decoder Reduction The core idea is to reduce the complexity of the decoder stage in Booth multipliers. This is typically the most computationally intensive part of the multiplier, responsible for determining the sign and magnitude of each partial product.

Abstract

Current approximate Booth multipliers fall short when compared to more advanced approximate multipliers like truncation-based logarithmic models. This study presents an innovative approximation strategy for Booth multipliers that achieves low error rates while utilizing fewer Booth decoders than conventional designs. The newly developed 16-bit BD16.4 approximate Booth multiplier demonstrates significant advantages over leading approximate logarithmic and higher-radix Booth multipliers in terms of error reduction and efficiency. Furthermore, the 8-bit variants also show marked improvements relative to existing logarithmic multipliers. Through neural network inference testing, the proposed approximate multipliers exhibit nearly equivalent inference accuracy compared to exact Booth multipliers and contemporary logarithmic multipliers. The findings reveal considerable decreases in Power-Delay-Product for both 16-bit and 8-bit configurations when compared to exact and approximate logarithmic multipliers.

Keywords— Booth multipliers, approximate computing, convolutional neural networks, logarithmic multipliers, leading one detection

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Tool: Xilinx Vivado

· HDL: Verilog

Learning Outcomes

· Understanding Approximate Computing Concepts

· Analysing the Architecture of Approximate Booth Multipliers

· Evaluating Trade-offs Between Efficiency and Error Rates

· Implementing Filtration Logic in Digital Design

· Applying Truncation Techniques for Error Management

· Recognizing the Role of Encode Selection in Multiplier Performance

· Exploring Applications of Approximate Multipliers in Real-World Scenarios

· Developing Skills in Resource Optimization for Computing Hardware

Demo Video

https://youtu.be/UzjLhR0jxOA?si=MjCSaQtKgm5Yqp-A

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice