Decoder Reduction Approximation Scheme for 8-Bit Booth Multipliers

The objective of the “Decoder Reduction Approximation Scheme for 8?Bit Booth Multipliers” is to introduce a novel decoder reduction approximation (DRA) scheme for Booth multipliers that significantly improves hardware efficiency by reducing the number of Booth decoders required (e.g., to N/4 instead of the traditional N/2) while maintaining low error rates, thereby achieving reductions in power?area product and power?delay product with minimal impact on accuracy for error?tolerant applications such as neural network inference.