DeBAM: Decoder Based Approximate Multiplier for Low Power Applications

Approximate computing has emerged as a viable method for designing power-efficient computing systems, especially for applications that can tolerate controlled levels of error, such as image processing and data compression. These applications often have inherent resilience to inaccuracies, allowing certain levels of error without significant degradation in output quality. In this context, data path units like multipliers can be approximated to save power without compromising the essential functionality.

This paper proposes a novel 8-bit multiplier design based on decoder logic, which reduces the partial products generated in the computation process. By minimizing the number of partial products, the design not only lowers the hardware complexity but also substantially reduces power consumption. The proposed approximate multiplier achieves an impressive 40.96% reduction in power consumption compared to traditional, accurate multipliers, and a 22.30% reduction when compared to existing approximate multipliers. To assess the design’s effectiveness, comprehensive simulations are performed on image sharpening and data compression algorithms, chosen due to their high error tolerance. Simulation results demonstrate that the proposed multiplier maintains acceptable error levels while achieving notable power savings. Furthermore, analysis on hardware area and delay suggests that this design can offer a balanced trade-off between power efficiency, area, and computational accuracy, making it highly suitable for low-power, error-tolerant applications.