Data Retention based Low Leakage Power TCAM for Network Packet Routing

Also Available Domains Cadence EDA|Core Memories|Cadence EDA

Project Code :TVPGTO62

Objective

The main objective of this paper is to reduce the leakage power for data retention based ternary content addressable memory and it can be reduced by using the continuous feature of mask data.

Abstract

In this project, a new state preserved technique, named Data Retention based TCAM (DR-TCAM), is proposed to reduce the leakage power dissipated in the TCAM memory. The Ternary Content Addressable Memory (TCAM) is widely used in the routing table due to its high lookup performance. However, a large number of transistors would cause the power consumption of TCAM to be considerable. According to the continuous feature of mask data, the DR-TCAM can dynamically adapt the power source of mask cells so as to reduce the TCAM leakage power. Particularly, the mask data wouldn’t be destroyed in the DR-TCAM. The simulation results show that the DR-TCAM performs better than the state of the art works. When compared to the traditional TCAM design, the DR-TCAM dissipates less power. The proposed design implemented using 180nm technology in Tanner EDA tool.

Keywords: Ternary Content Addressable Memory (TCAM), low leakage power, mask data.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Tanner EDA
Technology files:180nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Introduction to Content addressable Memories
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Importance of static power consumption in lower technology nodes
Static power reduction techniques
Transistor level design for TCAMS
How to design low power, high speed area efficient transistor level circuits?
Scope of TCAM in today’s world
Applications in real time
Tanner EDA tool for design and simulation
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Arithmetic Core
DSP Core
Communications and Crypto Core
Design for Testability
Nano Technology

Back End Domains

Low Power VLSI
Transistor Logic
Core Memories

Tools

FPGA
Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA

Others

Matlab Interfacing