Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm

Also Available Domains DSP Core|Xilinx ISE

Project Code :TVMATO307

Objective

This paper suggests three topologies for the LMS adaptive filter in light of these findings: There are three different designs: (i) Design 1 has no adaptation delays, (ii) Design 2 has just one adaptation delay, and (iii) Design 3 has two adaptation delays.

Abstract

In order to derive its architectures for high-speed and low-complexity implementation, this study gives a rigorous analysis of the least-mean-square (LMS) adaptive filter's critical path. It is demonstrated that the direct-form LMS adaptive filter offers substantially faster convergence and smaller register complexity while having almost the same critical path as its transpose-form equivalent. From the critical-path evaluation, it is further demonstrated that, in most practical circumstances, no pipelining is needed to build a direct-form LMS adaptive filter. In contrast, cases where a very high sampling rate is required can be realised with a very tiny adaptation delay. This paper suggests three topologies for the LMS adaptive filter in light of these findings:

There are three different designs: (i) Design 1 has no adaptation delays, (ii) Design 2 has just one adaptation delay, and (iii) Design 3 has two adaptation delays. Design 1 utilises the smallest area and the EPS, or minimum energy per sample. The best direct-form structures now in use require 41.9% more EPS and 80.4% more area than Design 1. While offering nearly twice and three times the MUF at a cost of 55.0% and 60.6% more area, Designs 2 and 3 use a little bit more EPS than Design 1 does.

Index Terms—Adaptive filters, critical-path optimization, least mean square algorithms, LMS adaptive filter

 

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

·         Xilinx ISE/Vivado

Hardware Requirements:

·         Microsoft® Windows XP

·         Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

·         512 MB RAM

·         100 MB of available disk space

Learning Outcomes

  • Basics of Digital Electronics
  • VLSI design Flow
  • Introduction to filters
  • Writing Verilog code.
  • Introduction to LMS adaptive filter.
  • Knowledge on implementation of LMS adaptive filter with delays.
  • Applications in real time

·         Xilinx tool for writing code, synthesis and simulation

·         Solution providing for real time problems

·         Project Development Skills:

o   Problem Analysis Skills

o   Problem Solving Skills

o   Logical Skills

o   Designing Skills

o   Testing Skills

o   Debugging Skills

o   Presentation Skills

o   Thesis Writing Skills

 

 

 

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