Counter Based Low Power, Low Latency Wallace Tree Multiplier using GDI Technique for On-chip Digital Filter Applications

This paper represents a new design of a low power, low latency Wallace tree multiplier. Wallace Tree algorithm is one of the most commonly used operations in modern days DSP applications as it can provide a fast and area efficient strategy for higher operand multiplication. For higher bits of multiplications the addition operation of partial products includes greater delay and complexity. In this present communication a number of techniques are applied in the
partial products addition circuitry to optimize the area delay and speed of the Wallace multiplier. Proposed Design is synthesized for 4x4 bit multiplication using standard CAD tool design compiler in 250nm process technology. Simulation
results show that the proposed multiplier design has the best power and delay results as compared to other available multipliers.