Convolution and Deconvolution using Vedic Mathematics

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVPGFE175

Abstract


Convolution and Deconvolution is having wide area of application in Digital Signal Processing. As in DSP Convolution and Deconvolution of long sequences is often required in many applications. Convolution helps to estimate the output of a system with arbitrary input, with knowledge of impulse response of the system. Linear systems characteristics are completely specified by the systems impulse response, as governed by the mathematics of convolution. Primary requirement of any application to work fast is that increase the speed of their basic building block. Multiplier and Divider is the heart of convolution and Deconvolution respectively. It is most important but, slowest unit of the system and consumes much time in the system. Many methods are invented to improve the speed of the Multiplier and Divider, amongst all Vedic Multiplier and Divider is under focus. Because, of faster working and low power consumption. In this paper the speed of Convolution and Deconvolution module is increased using Vedic multiplier and Divider.

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Specifications

Hardware requirement

             Processor               -    Pentium –III

 

Speed                                -    1.1 GHz

RAM                                 -    1 GB (min)

Hard Disk                          -   40 GB

Floppy Drive                     -    1.44 MB

Key Board                         -    Standard Windows Keyboard

Mouse                                -    Two or Three Button Mouse

Monitor                              -    SVGA

 

Software requirements

Operating System            :Windows95/98/2000/XP/Windows7

 

Front End                          :   Modelsim 6.3 for Debugging and Xilinx 14.3 for                     Synthesis and Hard Ware Implementation

 

This software’s where Verilog source code can be used for design implementation.

Learning Outcomes

  • Basics of Digital Electronics
  • Signals and Systems
  • Verilog HDL
  • RTL Designing Skills
  • Debugging Skills

Demo Video

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