Convolution and Deconvolution using Vedic Mathematics

Also Available Domains DSP Core|Xilinx ISE

Project Code :TVMATO396

Specifications

Hardware requirement

             Processor               -    Pentium –III

 

Speed                                -    1.1 GHz

RAM                                 -    1 GB (min)

Hard Disk                          -   40 GB

Floppy Drive                     -    1.44 MB

Key Board                         -    Standard Windows Keyboard

Mouse                                -    Two or Three Button Mouse

Monitor                              -    SVGA

 

Software requirements

Operating System            :Windows95/98/2000/XP/Windows7

 

Front End                          :   Modelsim 6.3 for Debugging and Xilinx 14.3 for                     Synthesis and Hard Ware Implementation

 

This software’s where Verilog source code can be used for design implementation.

Learning Outcomes

  • Basics of Digital Electronics
  • Signals and Systems
  • Verilog HDL
  • RTL Designing Skills
  • Debugging Skills

Demo Video

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