Concurrent Error Detectable Carry Select Adder with Easy Testability

Also Available Domains Cadence EDA|Design for Testability|Xilinx Vivado

Project Code :TVPGTO442

Objective

The main objective of this work is to use the Binary to Excess-1 Converter (BEC) to achieve high speed and low power consumption instead of the Ripple carry Adder in the regular Carry Select Adder.

Abstract

A concurrent error detectable adder with easy testability is proposed. The proposed adder is based on a multi-block carry select adder. Any erroneous output of the adder caused by a fault modeled as a single stuck-at fault can be detected by comparing the predicted parity of the sum with the parity of the sum, i.e., the XORed value of the sum bits, and comparing the duplicated carry outputs. The adder is also testable with only 10 input patterns under single stuck-at fault Model. This property eases detection of a fault before the occurrence of a second fault. Both the concurrent error detects ability to detect erroneous results and the easy testability to find a fault during operation is important for realizing reliable systems. Both the concurrent error delectability and the easy testability of the proposed adder are proven. A 32-bit adder has been designed. Its hardware overhead is about 70%. Its concurrent error detects ability and 100% test coverage through the 10 patterns has been confirmed by fault simulation.

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