Compressor Based 8 x 8 Bit Vedic Multiplier using Reversible Logic

Also Available Domains Arithmetic Core|Xilinx ISE

Project Code :TVPGTO335

Abstract

Reversible logic gates became very importantand computing paradigm having its applications in lowpower CMOS technologies and Quantum computing. Reversible logics are used to reduce the depth of the circuits. This paper introduces a newarchitecture of 4:2 Compressorbased Vedic 8x8 bitMultiplier using reversible logic and is compared withconventional multipliers using Reversible logic and itwas observed that the parameters like HardwareComplexity, power and Delay are improved over otherReversible multipliers. The design is simulated,synthesized and power estimation was done using Xilinx 14.3.

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Specifications

Hardware requirement

Processor - Pentium –III

Speed - 1.1 GHz

RAM - 1 GB (min)

Hard Disk - 40 GB

Floppy Drive - 1.44 MB

Key Board - Standard Windows Keyboard

Mouse - Two or Three Button Mouse

Monitor - SVGA

Software requirements

v Operating System :Windows95/98/2000/XP/Windows7

v Front End : Modelsim 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation

v This software’s where Verilog source code can be used for design implementation.

Learning Outcomes

Basics of Digital Electronics
Verilog HDL
RTL Designing
Debugging Skills

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing