Comparative Analysis of XOR Implementation using CMOS Logic, Domino Logic - Keeper Technique
Also Available Domains Cadence EDA
Objective
The objective of this project is to design and perform a comparative analysis of XOR gate implementations using CMOS logic and Domino Logic with the keeper technique. It focuses on evaluating the performance differences in terms of speed, power consumption, and area between conventional CMOS and Domino Logic designs. The designs will be simulated to verify functionality and measure key parameters such as propagation delay, dynamic power, and robustness. Comparative study will highlight the advantages and trade-offs of each approach for high-speed digital circuits. The overall goal is to identify the most efficient XOR gate implementation suitable for modern VLSI and high-performance digital applications.
Abstract
Abstract:
As technology continues to scale and advance, achieving the primary goals of design i.e., low power consumption and faster circuitry have become more feasible. The continuous advancement of technology scaling enables significant reductions in power consumption, a critical objective in digital logic design. Power consumption in digital circuits primarily depends on factors such as supply voltage, the number of transistors used, and transistor scaling. While CMOS technology predominantly relies on inversion logic using NAND and NOR structures, alternative logic design methodologies can optimize transistor usage. Traditional XOR gate designs require multiple transistors; however, this paper presents methodologies for 2-input XOR and 4-input XOR gate implementations using CMOS logic, Domino logic (Keeper Technique) in 90nm technology. The proposed Domino Logic design achieves reduced power consumption compared to conventional CMOS XOR implementations.NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Demo Video
Request for Video
Paper PublishingRequest Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
