Comparative Analysis of XOR Implementation using CMOS Logic, Domino Logic - Keeper Technique

The objective of this project is to design and perform a comparative analysis of XOR gate implementations using CMOS logic and Domino Logic with the keeper technique. It focuses on evaluating the performance differences in terms of speed, power consumption, and area between conventional CMOS and Domino Logic designs. The designs will be simulated to verify functionality and measure key parameters such as propagation delay, dynamic power, and robustness. Comparative study will highlight the advantages and trade-offs of each approach for high-speed digital circuits. The overall goal is to identify the most efficient XOR gate implementation suitable for modern VLSI and high-performance digital applications.