Also Available Domains Nano Technology|Transistor Logic|Low Power VLSI
To evaluate and compare the performance of 8T, 10T, and 12T SRAM cell architectures implemented using realistic CNTFET models in order to: Analyze read and write stability (Static Noise Margin) Compare power consumption, including leakage and dynamic power Study area overhead and transistor count trade-offs Assess read/write delay and reliability at scaled technology nodes Examine robustness to process variations and low-voltage operation
Conventional SRAM cells face serious challenges in terms of power consumption, stability, and process variations. Carbon Nanotube Field-Effect Transistors (CNTFETs) have emerged as a promising alternative due to their superior electrical characteristics and excellent performance at low supply voltages. This paper presents a comparative analysis of 8T, 10T, and 12T realistic CNTFET-based SRAM cells to evaluate their suitability for low-power and reliable memory applications. All SRAM architectures are designed using a realistic CNTFET model and analyzed under identical operating conditions. Key performance parameters such as static noise margin, read and write stability, leakage power, access delay, and energy consumption are investigated. The results show that the 8T SRAM cell achieves lower power and area efficiency, the 10T SRAM cell provides a balanced trade-off between stability and performance, and the 12T SRAM cell offers the highest robustness against read disturbance and process variations at the cost of increased area.
Index Terms— CNTFET, Static Random-Access Memory (SRAM), 8T SRAM, 10T SRAM, 12T SRAM, Low-Power Memory, Near-Threshold Operation, Read Stability, Write Margin, Static Noise Margin (SNM), Process Variations.
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Software Requirements:
· Cadence tool
· Technology files: 45nm
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes: