Circuit implementation of on-chip trainable spiking neural network using CMOS

The objective of “Circuit Implementation of On?Chip Trainable Spiking Neural Network Using CMOS Based Memristive STDP Synapses and LIF Neurons” is to develop and demonstrate a full CMOS transistor?level spiking neural network (SNN) that integrates memristive STDP synapse circuits and leaky integrate?and?fire (LIF) neurons to enable on?chip training and classification without external CPUs/GPUs, achieving energy?efficient neuromorphic processing with pattern recognition capability using standard CMOS technology.