Charge-sensitive amplifier design for high-speed interface readout front-end ASICs

This work addresses the design of Charge-Sensitive Amplifiers (CSAs) and the impact of peaking time on high-speed interface readout front-end ASICs for 3D pixel detectors that require high timing precision. The performance of various CSA architectures is evaluated across several process nodes, including 180 nm CMOS, 130 nm SiGe BiCMOS, 65 nm CMOS, and 22 nm FD-SOI CMOS, to compare the effects of technology scaling. Simulations of peaking time, charge gain, noise, and bandwidth are conducted for all implemented CSAs, identifying the best-performing CSA for high-speed and high-timing precision readout ASICs. Additionally, a complete readout chain capable of resolving particles with time precision better than 200 ps is designed and simulated. The resulting readout ASIC demonstrates a Time-Walk performance of ≤ 180 ps for input charges ranging from 6.3 to 10 ke−, with an equivalent noise charge of approximately 570 e−.