Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA

Also Available Domains Design for Testability|Xilinx ISE

Project Code :TVPGTO392

Objective

The main aim of this work is to generate random number sequences in security applications. In this paper, various chaotic circuits for TRNG are reviewed and design a chaotic oscillator and compared it with ring oscillator based TRNG for better randomness

Abstract

In this project, various TRNG architectures are reviewed and implemented. We have implemented Ring Oscillators by varying number of inverters and also analyzed its performance. It was seen that Ring Oscillators TRNG with 24 inverters gave the best performance even without post-processing. We have also reviewed various chaotic circuits for TRNG and implemented chaotic oscillator based TRNG and compared it with ring oscillator based TRNG.

To improve the randomness using the chaotic circuit, we used a circuit having chaos in the ring oscillator. The effectiveness of the proposed design is synthesized and simulated using Xilinx Vivado software.

Keywords: True Random Number Generator (TRNG), Chaotic ring oscillator, Flip-Flop.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx Vivado
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to TRNGS
Role of TRNGS in Security systems
Knowledge on ring oscillator based TRNG
Drawbacks of ring oscillators based TRNGS
Introduction to Chaotic ring oscillator
Design of True random number Generator using Chaotic ring oscillator
How high performance is achieved in Residue number system
How to achieve high speed, Low power and Area efficiency?
Scope of approximation concept in today’s world
Applications in real time
Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing