Carry look ahead adder using adiabatic logic

In modern digital circuits, designers focus on key factors such as high speed, high throughput, compact silicon area, and low power consumption. Full adders play a crucial role in various applications, including subtraction, counting, multiplication, filtering, Digital Signal Processor (DSP) architectures, and microprocessors. Designing a carry look-ahead adder (CLA) is particularly noteworthy due to its high-speed performance. This project involves implementing the CLA using 180nm CMOS technology within the Tanner EDA tool. Both static CMOS and adiabatic logic are analyzed and implemented. The power consumption of each logic type is estimated and compared. Results indicate that adiabatic logic consumes less power, while static CMOS logic provides lower delay.