Calculator Interface Design in Verilog HDL using MIPS32 Microprocessor

This is implemented using the MIPS32 (Microprocessor without Interlocked Pipelined Stages) processor, which has a five-stage pipelined architecture and 32 registers, using Verilog HDL in the Model Sim software. An interface module is created in which the processor module is instantiated to provide the two-phase clock input and control signals to the processor and for the user to inputs. Based on the choice of operation and the operands provided, the corresponding operation would be executed and the result would be displayed. The assembly language code for each operation is coded as 32-bit instructions within the interface module and stored in the memory. The processor fetches, decodes, and executes these instructions and stores the result in one of the registers, which is then displayed to the user using the interface.