This proposes a new multiplier architecture based on the algorithm that adapts the approximate compressor from the existing and proposed compressors’ set to reduce error in the respective partial product columns.
Abstract—Approximate computing is an evolving paradigm that aims to improve the power, speed, and area in neural network applications that can tolerate errors up to a specific limit. This letter proposes a new multiplier architecture based on the algorithm that adapts the approximate compressor from the existing and proposed compressors’ set to reduce error in the respective partial product columns. Further, the error due to the approximation in the proposed multiplier is corrected using a simple error-correcting module. Results prove that the power and power–delay product (PDP) of an 8-bit multiplier is improved by up to 39.9% and 43.6% compared with the exact multiplier and 27.5% and 23.9% compared to similar previous designs. The proposed multiplier is validated using image processing and neural network applications to prove its efficacy.
Index Terms—Approximate compressor, approximate computing, neural network application, partial product reduction (PPR)
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Software Requirements:
VIVADO 2018.3
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
· VIVADO for design and simulation
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills