BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circuit

Project Code :TVMABE243

Objective

The primary objective of designing a BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circuit is to enhance the reliability and stability of digital systems, especially under conditions where they are exposed to various forms of stressors such as voltage fluctuations, temperature changes, and radiation effects. This circuit aims to mitigate the adverse effects of these stressors on the performance and longevity of digital device

Abstract

This letter introduces a new voltage-bootstrapped Schmitt trigger (VB-ST) circuit designed to be resilient against BTI effects, with enhancements in noise margin, leakage power, and rail-to-rail voltage. The circuit utilizes a single NMOS transistor, effectively mitigating the aging effects such as Negative Bias Temperature Instability (NBTI). The reliability assessment of the circuit focuses on critical charge and soft error rate ratio (SERR), revealing significant improvements: the critical charge is enhanced by 6.31× and SERR is reduced by 84.0% compared to a CMOS circuit operating at 0.4V supply voltage. Evaluating the proposed design for reliability and robustness, the quality factor (QF) is employed as a performance metric, demonstrating a remarkable 144× improvement over the CMOS circuit

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Tool: Cadence Virtuoso
Technology: GPDK 45nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Learning Outcomes:

· Introduction to Analog circuits

· Understanding of Circuit Design Challenges

· Necessity of Schmitt trigger.

· Advantages & Applications of Schmitt trigger

· Advanced Semiconductor Physics

· Knowledge on voltage circuits

· Design of Schmitt trigger.in Cadence

· Analysis of simulation results & Outputs

· Usage voltage boots strapping circuits

· Application of Analog and Mixed-Signal Techniques

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice