Block-Based Carry Speculative Approximate Adder for Energy-Efficient Applications

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVREFE19_18

Objective

In this paper, a low energy consumption block-based carry speculative approximate adder is proposed.

Abstract

In this paper, a low energy consumption block-based carry speculative approximate adder is proposed. Its structure is based on partitioning the adder into some non-overlapped summation blocks whose structures may be selected from both the carry propagate and parallel-prefix adders. Here, the carry output of each block is speculated based on the input operands of the block itself and those of the next block. In this adder, the length of the carry chain is reduced to two blocks (worst case), where in most cases only one block is employed to calculate the carry output leading to a lower average delay. In addition, to increase the accuracy and reduce the output error rate, an error detection and recovery mechanism is proposed. The effectiveness of the proposed approximate adder is compared with state-of-the-art approximate adders using a cost function based on the energy, delay, area, and output quality. The results indicate an average of 50% reduction in terms of the cost function compared to other approximate adders.

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Block Diagram

Specifications

Xilinx ISE 14.7 for Synthesis

Learning Outcomes

Basics of Digital Electronics, Parallel prefix adders, Verilog

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