BCD Adder Designs Based on Three-Input XOR and Majority Gates

Abstract:

Many new approaches are capable of natively realizing majority-of-three (MAJ) gates. There are several effective XOR designs that are directly derived from the physical properties of new approaches, even though improved gates like exclusive-OR (XOR) gates may be accomplished using various MAJ gates. In this paper, we introduced multi-digit exclusive-OR (XOR3) and MAJ adder designs for binary coded decimal (BCD) adders with three inputs. In computers for business, industry, and finance, BCD adder is frequently used. After developing Verilog code to implement the designs, we used the Xilinx Vivado tool to simulate and synthesize the designs. Various binary adders, such the RCA-BCD and PBA-BCD adders, are used to validate the suggested logic representations. The addition of XOR3 gates makes it possible to create compact logic representations, which has a good impact on both area and latency. The suggested 1-digit BCD adder has reduced area and delay when compared to the best current designs.

Keywords: Maj, XOR, BCD, binary adder, RCA-BCD, PBA-BCD, Xilinx Vivado.