ASIC Implementation of Distributed Arithmetic Based FIR Filter using RNS for High Speed DSP systems

Also Available Domains DSP Core|Xilinx ISE

Project Code :TVMATO498

Objective

This proposed work aims to implement memory less distributed arithmetic (MLDA) architecture in a finite impulse response filter with a residual number system. Through this design, it enhances the speed of the systems

Abstract

This project presents an efficient implementation of memory less distributed arithmetic (MLDA) architecture in finite impulse response filter with residual number system. The input data and filter coefficients of MLDA are in residue number form and the output data from MLDA is converted into binary form using Chinese remainder theorem.

In addition, compressor adders are used to reduce the area. For real time validation, the proposed design has been simulated and synthesized

using Xilinx Vivado.

Keywords: Residual number system, Distributed arithmetic, Finite impulse response, Chinese remainder theorem

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx Vivado
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to Distributed Arithmetic Circuits
Role of Distributed arithmetic In Fir Filters
Introduction to Residue number system
How high performance is achieved in Residue number system
How to achieve high speed, Low power and Area efficiency?
Scope of approximation concept in today’s world
Applications in real time
Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice