Area–Time–Power Efficient FFT Architectures based on Binary-Signed-Digit CORDIC

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE360

Objective

The main aim of this project is to improve the speed of cordic, which is used in FFTS. An improved version of the composed CORDIC, which aims to achieve speep by employing the posibit-negabit BSD encoding.

Abstract

In this project, a RIC based BSD CORDIC is proposed. In a Fast Fourier transform (FFT) major demerit is the usage of complex multipliers. CORDIC is the most prevalent method to replace the complex multipliers of FFTs. In order to enhance the speed of CORDIC, redundant binary signed-digit (BSD) encodings can be utilized, so-called BSD-CORDIC. The main goal of this paper is to improve the efficiency of BSD-CORDIC-based FFT. The redundant improved composed (RIC) CORDIC is proposed as a novel BSD-CORDIC. The main idea behind the RIC CORDIC lies in prior determination of the required iterations in such a way that the maximum number of iterations is reduced, which results in speedup and decrease in hardware resources. Also, some of the iterations still can be skipped, which leads to further reduction in the power consumption. The synthesis results demonstrate that the FFT based on the RIC BSD-CORDIC enhances speed, power consumption, and area overhead.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to FFT algorithms
About DFT algorithm
Knowledge on multiplier circuits
Different BSD encodings
Knowledge on complex multipliers
About CORDIC algorithm
Applications in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice