Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS

This work presents the design of an area-efficient and low-power 8-transistor (8T) Compute-SRAM bitcell tailored for digital compute-in-memory (CIM) macros in 22nm CMOS technology. With the rapid growth of data-intensive applications such as artificial intelligence, machine learning, and edge computing, conventional von Neumann architectures face significant limitations due to excessive data movement between memory and processing units. Compute-in-memory (CIM) has emerged as a promising solution to overcome this bottleneck by enabling computation directly within memory arrays.

In this design, an optimized 8T SRAM bitcell is developed to support both reliable data storage and in-memory logic operations. The proposed bitcell separates read and write paths to enhance stability and reduce read disturbance, while additional transistors enable efficient computation within the memory array. The design focuses on minimizing area overhead and reducing power consumption through optimized transistor sizing and reduced switching activity. Implemented in 22nm CMOS technology, the proposed bitcell demonstrates improved energy efficiency, reduced delay, and enhanced robustness compared to conventional 6T SRAM cells and existing CIM designs. This makes it highly suitable for next-generation low-power, high-performance digital compute-in-memory systems.

 

Keywords

 

Compute-In-Memory, 8T SRAM, Low Power, Area Efficient, 22nm CMOS, Digital CIM, Memory Bitcell Design