Area Delay and Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE38

Objective

The main aim of this work is to develop the area and delay efficient in place RFFT. This can be achieved by partitioning the storage unit into several banks of smaller sizes to resolve the memory access conflicts by concurrent data-swapping between the banks.

Abstract

Efficient computation of real-valued fast Fourier transform (RFFT) has received significant attention in recent years due to its several applications in conventional digital signal processing and other emerging areas. In-place RFFT architectures are gaining popularity due to their lower hardware complexity compared with pipeline architectures. In this paper ,we have designed a new butterfly unit is proposed in which 8 point butterfly unit is implemented by two 4 point FFT unit with simple butterfly structure and low memory requirement. So when compare to the previous method the proposed method consume less area over ahead and less delay.

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Block Diagram

Specifications

Software Requirements:

Xilinx ISE/Xilinx Vivado Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding.
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Different types of FFT

DIT-FFT
DIF-FFT

About Butterfly Processing Element
FFT implementations
Single-path Delay Commutator
Multi-Path Delay Commutator
Radix-2,Radix-4 & Radix-8 FFT architectures
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice