Area Delay and Energy Efficient Multi-Operand Binary Tree Adder
Also Available Domains Xilinx Vivado|Xilinx ISE
Objective
The main objective of this project is to develop an efficient binary tree adder design. To improve the efficiency, a new logic formulation has been done to RCA and based on this RCA 8 operand BTA for n bit is designed.
Abstract
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx ISE/ Xilinx Vivado Tool
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Introduction to Arithmetic circuits
- Knowledge on adder circuits
- Different MOA’s
- Knowledge on BTA adder designs
- Applications in real time
- Xilinx ISE 14.7/Xilinx Vivado for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
Paper Publishing
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