Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput Fiber-Optical Communications

Also Available Domains Communications and Crypto Core|Xilinx Vivado|Xilinx ISE

Project Code :TVPGFE103

Objective

The main objective of this project is to improve the high throughput and reduce the errors in the encoder. This encoder is designed with a multistage pipelined architecture by splitting the parity generation matrix and precomputing partial parity bits for the next staircase block while generating the current staircase block

Abstract

The continuous advancements in optical communication channels have propelled the development of new error-correcting codes, e.g., staircase codes, which belong to a class of Forward Error correction codes. The staircase code is a new in-line error-correcting code that promises near-capacity performance. This project presents a VLSI architecture of a high throughput, low-latency staircase forward error correction (FEC) encoder. The designed encoder achieves low latency and memory overhead by splitting the parity generation matrix and pre-computing partial parity bits for the next staircase block while generating the current staircase block. The proposed encoder is designed with a multistage pipelined architecture that enables high efficiency in terms of throughput and area.

Keywords: Forward Error Correction (FEC), staircase codes, Parity Generation, Fiber- Optical Communication

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