Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput Fiber-Optical Communications

Also Available Domains Cadence EDA|Communications and Crypto Core|Xilinx Vivado

Project Code :TVPGTO399

Objective

The main objective of this project is to improve the high throughput and reduce the errors in the encoder. This encoder is designed with a multistage pipelined architecture by splitting the parity generation matrix and precomputing partial parity bits for the next staircase block while generating the current staircase block

Abstract

The continuous advancements in optical communication channels have propelled the development of new error-correcting codes, e.g., staircase codes, which belong to a class of Forward Error correction codes.

The staircase code is a new in-line error-correcting code that promises near-capacity performance. This project presents a VLSI architecture of a high throughput, low-latency staircase forward error correction (FEC) encoder. The designed encoder achieves low latency and memory overhead by splitting the parity generation matrix and pre computing partial parity bits for the next staircase block while generating the current staircase block.

The proposed encoder is designed with a multistage pipelined architecture that enables high efficiency in terms of throughput and area. The effectiveness of the proposed method is designed using Xilinx ISE 14.7

Keywords: Forward Error Correction (FEC), staircase codes, Parity Generation, Fiber- Optical Communication

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE 14.7
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to staircase Encoders
Role of stair case encoders in optical communications
Knowledge on Bit matrix multipliers and adders
Introduction to memories
Knowledge on parity Generation
Knowledge on parity Checking
How to achieve high speed, Low power and Area efficiency?
Advantages of staircase Encoders
Scope of Stair case Encoders in today’s world
Applications in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing